FPGA Design...

Where we discuss new analog design ideas for Pro Audio and modern spins on vintage ones.
Crusty
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FPGA Design...

Post by Crusty »

Dipping my toes into FPGA design - I need a simple, high-speed multichannel pulse generator, and it looks like FPGA is the only way to go. Anyone reccomend any books on the subject? Amazon lists dozens...

Thanks!
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mediatechnology
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Re: FPGA Design...

Post by mediatechnology »

Crusty - I'd PM jdbakker on that one.

Wayne
waveterm
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Re: FPGA Design...

Post by waveterm »

For VHDL, here is a way to start learning for free: http://tams-www.informatik.uni-hamburg. ... okbook.pdf

I recommend the author's latest book if you find his style to your liking.

It is important to remember that many things described in the language are not synthesizable, but rather are used for test bench development. Also, remember that the language is used to describe hardware and not sequentially executed software.
Crusty
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Re: FPGA Design...

Post by Crusty »

Thanks for the link - I always like to see "Cookbook" in a title. It's reassuring to me. I'll keep in mind comments about context as I read it.

Wayne, I'll p.m. Mr. JDB., good idea.
Andy Peters
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Re: FPGA Design...

Post by Andy Peters »

Crusty wrote:Dipping my toes into FPGA design - I need a simple, high-speed multichannel pulse generator, and it looks like FPGA is the only way to go. Anyone reccomend any books on the subject? Amazon lists dozens...
Some comments from an FPGA guy of some fifteen years experience ...

Any book on FPGA design is probably outdated the moment it's published. The tools change pretty quickly. But having said that, the basics are straightforward. Remember that synchronous descriptions are best. Don't try to outsmart the synthesizer. Don't try to take a design built out of TTL gates and instantiate it in VHDL. Pay attention to the templates in the synthesis guide (all the while realizing that Xilinx' examples still use the obsolete std_logic_arith libraries!). Basically, VHDL is not a programming language: it is a hardware description language, so THINK HARDWARE. Remember that everything executes in parallel.

I like Peter Ashenden's "Designer's Guide To VHDL," which isn't strictly targeted to FPGAs or synthesis, but it's a very complete overview of the language and I still find it useful. The Xilinx tools generally support VHDL'2002. If you're into Verilog, the Palnitkar book is very good, with the same caveats (and watch your blocking vs non-blocking assignments). Don't even bother with the schematic tools, not even for a top-level block diagram connecting HDL lower-level bits.

Hierarchical design is your friend. Smaller pieces are easier to simulate and debug. Don't try to make every single piece of logic its own entity, but do try to keep your entities reasonably small. Write a test bench for each entity and simulate them as you develop them.

On that last note: learn to write excellent test benches and SIMULATE your design. I know that there's sometimes an aversion to simulation ("real men do burn and crash"), but I've found that an hour creating a real VHDL test bench and simulating my design saves a day in the lab, and it's basically impossible to attach enough logic analyzer probes to a board to get a handle on what's going on. (Having said that, Xilinx' ChipScope is pretty excellent.) And your test benches shouldn't be the simple stupid "toggle a bit here and there" that the Xilinx simulator generates. If you're clever, the test bench emulates the peripheral hardware connected to your FPGA. An excellent introduction to simulation and verification is Janick Bergeron's book, "Writing Test Benches."

You will need to set timing and placement constraints. For most simple FPGA designs, your constraints file will have just a period constraint on the global clock and pinout (placement, slew rate/termination, I/O type) constraints. Don't bother with post-place-and-route back-annotated timing simulation. If your timing constraints are complete and you meet them, and if your functional simulation tells you that your logic is correct, the design will work.

The Xilinx ISE text editor sucks ass. Use emacs and its most-excellent VHDL mode, which has templates and tab completion and basically takes all of the fuss out of writing VHDL.

It might be worth spending the hundred bucks for one of the Avnet or Xilinx "starter kits."

Good luck, and feel free to PM or e-mail.

-a
Crusty
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Re: FPGA Design...

Post by Crusty »

Sounds like you have alot of experience using these parts. JDBakker recomended that I look into possibly using a CPLD instead for something as simple as I describe. Might be an easier learning curve too for me. This is all sort of "cart before the horse" anyway - I could experiment first with a microcontroller with a pwm output capability, and prove the concept before diving into these new areas...

A lot of good advice there, regardless of how I try to get it done. Thanks!
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JR.
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Re: FPGA Design...

Post by JR. »

Cheap micros can have two of more PWM built in but they are often linked to single common counter timebase. Of course you could always always roll any number of oddball outputs depending on timing precision required.

JR
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Crusty
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Re: FPGA Design...

Post by Crusty »

This is for a multi-channel chopper (audio frequencies), capable of 30-channels (or could be dual 15-channels), and I'd like a fairly high timebase (1MHz or so) so I can use simple output filters.

I'm not sure of timing precision needed yet, but they can be driven by the same clock source. (I am thinking timing precision will directly affect signal distortion?).16 bit resolution would be preferred.

That's why I was looking at FPGA (now CPLD) for the end solution, controlled by a micro. I can certainly use a micro with two or four channel pwm to see if the idea is worth the pursuit...
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JR.
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Re: FPGA Design...

Post by JR. »

Sorry I'm not sure what you mean by a chopper so can't speculate on a solution.

JR
Cancel the "cancel culture", do not support mob hatred.
Crusty
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Re: FPGA Design...

Post by Crusty »

In a nutshell, I wanted to try replacing the resistors in a passive filter (such as Twin-'T') with FET switches, and control the cutoff freq by varying the duty cycle...
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